1. Field of the Invention
The present invention relates to a semiconductor device and a method for fabricating the same, and more particular to, a Dynamic RAM (DRAM) semiconductor device and a method for fabricating the same.
2. Description of the Related Art
In general, as the integration concentration of DRAM semiconductor devices increases, it is desirable to form source/drain regions as shallow junction regions so as to ensure stability of a transistor. Also, it is required to form contacts having low resistance to source/drain regions in order to achieve high-speed operation of the transistor.
First, a conventional method for fabricating a DRAM semiconductor device having source/drain regions formed as shallow junction regions and low-resistance contacts will be described.
FIGS. 1 through 3 are views for explaining a method for fabricating a DRAM semiconductor device according to the conventional art. More specifically, FIGS. 1 through 3 are views of cell regions of the DRAM semiconductor device.
Referring to FIG. 1, a gate stack pattern 18 on a semiconductor substrate 10 in which a Trench Isolation Region (TIR) and a Active Region (AR) has been determined is formed. A silicon substrate is used for the semiconductor substrate 10. The gate stack pattern 18 is formed by sequentially stacking a gate electrode constructed with a gate dielectric film (not shown), a poly-silicon film 12 and a metal suicide film 14, and a capping film 16. The gate stack pattern 18 functions as a word line.
Next, an n− source/drain region 20 is formed in the AR of the semiconductor substrate 10 to be aligned with the gate stack pattern 18. The n− source/drain region 20 is formed as a shallow junction region by ion implantation with a shallow implantation depth and a low concentration of impurities by using n-type dopants such as phosphorus (P) or arsenic (As), if the semiconductor substrate 10 is a p-type silicon substrate.
After the formation of the n− source/drain region 20, a gate spacer 22 is formed on both sidewalls of the gate stack pattern 18. Then an interlayer dielectric film 24 is formed on the semiconductor substrate 10 so as to insulate the gate stack pattern.
Referring to FIG. 2, the interlayer dielectric film 24 is patterned by photolithography. Then an interlayer dielectric film pattern 24a having a contact hole 26 exposing the n− source/drain region 20 is formed.
Referring to FIG. 3, a barrier film 28 formed of Ti/TiN is formed on the wall of the contact hole 26. Then, pads 30a and 30b of a tungsten film are formed on the barrier film 28. The pad 30a is connected to a storage electrode during a subsequent process and the pad 30b is connected to a bit line during the subsequent process. After that, a DRAM semiconductor device is completed through a general processes such as a bit line forming process and a capacitor forming process or the like.
As described above, in a conventional method for fabricating a DRAM semiconductor device, a titanium silicide film is formed by a reaction of the n− source/drain region with the Ti film constituting the barrier film during a thermal process after the barrier film forming process. The Ti silicide film penetrates into the n− source/drain region so that the n− source/drain region is not able to become a shallow junction region and leakage current is increased during operation of the DRAM semiconductor device.